Complex electronic circuits are generally constructed of several conductive layers separated by insulating dielectric layers. The conductive layers are interconnected by electrically conductive pathways or vias through the dielectric. This multilayer construction allows significantly smaller circuit size than single layer circuit design.
In the production of a multilayer circuit, the conductive layer is generally printed onto the insulating layers. The conductive lines are very fine, in order to minimize circuit size. To assure the printing is accurate, and that subsequent layers are in the proper registration with lower layers, it is extremely important for the assembly to be dimensionally stable in the X-Y plane. Failure to create a dimensionally stable package results in shorted circuits, misaligned vias, and non-functioning circuits.
One method of creating dimensionally stable multilayer circuits is disclosed by Rellick in U.S. Pat. No. 4,806,188. In this method, a patterned conductive layer is applied to a dimensionally stable ceramic substrate, as depicted in FIG. 1A. The ceramic and conductive layer are then fired to consolidate the conductor layer, thereby providing a suitable surface for following layers. Next a dielectric tape is laminated over the conductor, vias are created and the assembly is refired. The vias are filled, fired, and another conductive layer is applied. The process is repeated until the desired number of layers are built up.
Firing is the most time consuming step in the process of manufacturing a multilayer circuit. Additionally, repeated firing negatively affects the printed conductor layer because the metallization tends to diffuse into the dielectric or contract causing incomplete circuitry. It is therefore desirable to minimize the number of times an assembly must be fired. Rellick suggested eliminating the firing step between forming and filling vias, as shown in FIG. 1B. He also suggested eliminating the firing step between filling vias and printing the conductive layer over the dielectric tape, as depicted in FIG. 1C, and eliminating both firing steps, as shown in FIG. 1D. However, Rellick does not suggest eliminating the first firing step which must occur between printing the conductor and laminating the dielectric tape to the conductor layer.
Elimination of the first firing step in the Rellick process typically results in poor lamination between the ceramic substrate and the dielectric tape layer and therefore an unacceptable multilayer circuit. One cause of such poor lamination is conductor height. When the conductive layer is fired as in Rellick's method, its height is reduced by approximately 50%. The dielectric tape laminated over the conductor can then more easily conform to this lower profile, fired, conductive layer than it can to a high profile, unfired, conductive layer. Therefore, not firing before applying the dielectric tape negatively impacts adhesion under Rellick's method.
Generally, poor adhesion during a lamination process is cured by increasing the laminating pressure. However, in Rellick's method, simply increasing pressure does not solve the poor adhesion problem and in addition creates a "high pressure defect" in the part. This defect is realized as a rough topography which reduces the accuracy of conductive patterns and via patterns in layers laminated over the hills and valleys of the effected assembly. The present invention overcomes these problems of poor lamination of dielectric tape to an unfired conductive layer, the "high pressure defect", and allows elimination of one or more firing steps when forming a multilayer circuit.